1. Field of the Invention
The present invention relates to liquid crystal displays, and more particularly to liquid crystal displays capable of preventing a difference in brightness from being generated between horizontal line blocks and a driving method thereof.
2. Description of the Related Art
Generally, liquid crystal displays (LCDs) control light transmittance characteristics liquid crystal material using electric fields to display pictures. Accordingly, LCDs typically include a LCD panel having a plurality of liquid crystal cells arranged in a matrix pattern and a drive circuit for driving the LCD panel.
The LCD panel includes a plurality of gate lines and a plurality of data lines arranged so as to cross one another, wherein the liquid crystal cells are defined by crossings of the gate and data lines. The liquid crystal display panel is further provided with a common electrode and a plurality of pixel electrodes for applying the electric fields to the plurality of liquid crystal cells. Each pixel electrode is connected to a respective data line via source and drain terminals of a switching device such as a thin film transistor (TFT). Gate terminals of the TFTs are connected to respective gate lines, allowing pixel voltage signals to be applied to lines of pixel electrodes.
The drive circuit includes a gate driver for driving the plurality of gate lines, a data driver driving the plurality of data lines, a timing controller for controlling the gate and data drivers, and a power supply for applying various drive voltages used by the LCD. The timing controller controls the drive timing of the gate and data divers while simultaneously applying a pixel data signal to the data driver. The power supply generates drive voltages such as a common voltage VCOM, a gate high voltage VGH, a gate low voltage VGL, etc., required by the LCD. The gate driver sequentially applies scan signals to the plurality of gate lines to sequentially drive the plurality of liquid crystal cells one line at a time. The data driver applies pixel voltage signals to the plurality of data lines whenever scan signals are applied to any one of the plurality of gate lines. Accordingly, the LCD controls the light transmittance characteristics of liquid crystal material by applying the electric field between the plurality of pixel electrodes and the common electrode in accordance with pixel voltage signals applied to the plurality of liquid crystal cells to display a picture.
The data and gate drivers include a plurality of integrated circuits (ICs) directly connected to the LCD panel. The data driver IC and the gate diver IC are either mounted onto a tape carrier package (TCP), capable of being connected to the LCD panel in a tape automated bonding (TAB) method, or are mounted directly onto the LCD panel in a chip-on-glass (COG) method.
Driver ICs, mounted to their respective TCPs and connected to the LCD panel via the TAB method, are connected to each other and receive external control signals and drive voltages via signal lines formed on a printed-circuit-board (PCB) connected to the TCP. Specifically, the data driver ICs are connected in parallel via signal lines formed on a data PCB. Accordingly, the data driver ICs commonly receive control signals and pixel data signals from the timing controller and receive drive voltages from the power supply. The gate driver ICs are connected in series via signal lines formed on a gate PCB. Accordingly, the gate driver ICs receive control signals from the timing controller and receive drive voltages from the power supply.
The driver ICs mounted directly to the LCD panel via the COG method are connected to one another via a line-on-glass (LOG) method where signal lines are mounted directly onto the LCD panel. Specifically, the signal lines are mounted directly onto a lower glass substrate of the LCD panel. Accordingly, the LOG signal lines receive control signals from the timing controller and receive drive voltages from the power supply.
Even when the aforementioned driver ICs are connected to the LCD panel via the TAB method, the LCD can be made thinner by eliminating the PCB and by adopting the LOG method. For example, gate driver ICs typically require a relatively small amount of signal lines. Accordingly, signal lines connected to the gate driver ICs, previously provided via the TAB method, are formed directly on the LCD panel and are connected in series to each other via the LOG method. As a result, the necessity of the gate PCB is eliminated, the gate driver ICs are connected in series via signal lines mounted directly on the lower glass substrate of the LCD panel, and the gate driver ICs commonly receive control signals and drive voltages (hereinafter referred to collectively as gate drive signals).
FIG. 1 illustrates a plan view of a line-on-glass (LOG) liquid crystal display (LCD) according to the related art.
Referring to FIG. 1, a related art LCD employing the use of LOG signal lines instead of a gate PCB, generally includes an LCD panel 1, a data PCB 12, a plurality of data TCPs 8 connected between a first side of the LCD panel 1 and the data PCB 12, a plurality of data driver ICs 10 mounted on respective ones of the data TCPs 8, a plurality of gate TCPs 14 connected to a second side of the LCD panel 1, and a plurality of gate driver ICs 16 mounted on respective ones of the gate TCPs 14.
The LCD panel 1 generally includes a lower substrate 2 supporting a thin film transistor (TFT) array and various signal lines including gate lines 20 and data lines 18, an upper substrate 4 supporting a color filter array. Liquid crystal material is injected between the lower substrate 2 and the upper substrate 4. As mentioned above, the LCD panel 1 includes a plurality of liquid crystal cells arranged in a matrix pattern and provided at crossings of the gate and data lines 20 and 18 to collectively form a picture display area 21. In an outer area of the lower substrate 2, located outside the picture display area 21, data pads are formed to extend from the plurality of data lines 18 and gate pads are formed to extend from the plurality of gate lines 20. Further, an LOG signal line group 26 may be formed within the outer area of the lower substrate 2 for transmitting gate drive signals to the gate driver ICs 16.
The data driver ICs 10 are mounted onto respective ones of the data TCPs 8 having input pads 24 and output pads 25 for electrically connecting to the data driver ICs 10. The input pads 24 of the data TCP 8 are electrically connected to output pads of the data PCB 12 while the output pads 25 are electrically connected to the data pads formed within the outer area of the lower substrate 2. A first data TCP 8 supports a gate drive signal transmission group 22, formed to electrically connect to an LOG signal line group 26 mounted onto the lower substrate 2. The gate drive signal transmission group 22 applies gate drive signals to the LOG signal line group 26 outputted by the timing controller and the power supply via the data PCB 12.
The data driver ICs 10 convert digital pixel data signals into analog pixel voltage signals and applies the analog pixel voltage signals to the plurality of data lines 18 in the LCD panel 1.
The gate driver ICs 16 are mounted onto respective ones of the gate TCPs 14 supporting a gate drive signal transmission line group 28 and output pads 30 for electrically connecting to the gate driver ICs 16. The gate drive signal transmission line group 28 is electrically connected to the LOG signal line group 26 on the lower substrate 2 and the output pads 30 are electrically connected to the gate pads formed within the outer area of the lower substrate 2.
The gate driver ICs 16 sequentially apply scan signals, such as a gate high voltage (VGH) signal, to the plurality of gate lines 20 in response to the output control signals. Further, the gate driver ICs 16 apply a gate low voltage (VGL) signal to the gate lines during the remainder of a horizontal period, excluding a period during which the VGH signal is applied.
The LOG type signal line group 26 generally consists of signal lines capable of transmitting drive voltages supplied from the power supply (e.g., a high logic voltage of the gate signal (gate high voltage) VGH, a low logic voltage of the gate signal (gate low voltage) VGL, a common voltage VCOM, a ground voltage GND and a power supply voltage VCC, etc.) and gate control signals supplied from the timing controller (e.g., a gate start pulse GSP, a gate shift clock signal GSC, a gate enable signal GOE, etc.).
Signal lines in the LOG signal line group 26 are formed in parallel in a fine pattern and occupies a relatively small amount of space (e.g., in a pad area arranged within the outer area of the lower substrate 2). Further, the LOG signal line group 26 is formed simultaneously with, and out of the same material as, a gate metal layer forming the plurality of gate lines 20. The gate metal layer typically includes a metal having a relatively high resistivity constant coefficient (0.046) such as AlNd. Accordingly, a resistance value of the LOG signal line group 26 is generally greater than a resistance value of the signal lines formed of thin copper in gate PCBs. Further, the resistance value of the LOG signal line group 26 is proportional to the length of the signal lines within the LOG signal line group 26. Accordingly, as the distance from the data PCB 12 increases, the resistance of the signal line increases to the point that the gate drive signals become undesirably distorted. As the gate drive signals become distorted, the picture quality displayed within the picture display area 21 becomes deteriorated as well.
FIG. 2 illustrates a difference in brightness between horizontal line blocks caused by a line resistor of the LOG signal group shown in FIG. 1.
Referring to FIG. 2, within the related art LCD, each of the LOG signal lines within the LOG signal line group 26 transmits gate high and low voltages VGH and VGL, respectively, and consists of first to third LOG type signal lines LVG1 to LVG3 each connected between a first data TCP 8 and a first to a third gate TCP 14A to 14C. The first to third LOG type signal lines LVG1 to LVG3 each have inherent line resistances a, b, c, respectively, proportional to their lengths and are connected to each other in series via the first to third gate TCPs 14A to 14C.
Accordingly, the first gate driver IC 16, mounted onto the first gate TCP 14A, is supplied with a first gate voltage VG1, including the gate high voltage VGH and the gate low voltage VGL, that is reduced in an amount proportional to the first line resistance (a) of the first LOG type signal line LVG1. The first gate voltage VG1 is applied to the gate lines of the first horizontal line block (A) via the first gate driver IC 16.
The second gate drive IC 16, mounted onto the second gate TCP 14B, is supplied with a second gate voltage VG2, including the gate high voltage VGH and the gate low voltage VGL, that is reduced in an amount proportional to the sum of the first and second line resistances (a+b) of the first LOG type signal line LVG1 and the second LOG type signal line LVG2, connected in series. The second gate voltage VG2 is applied to the gate lines of the second horizontal line block (B) via the second gate drive IC 16.
The third gate driver IC 16, mounted onto the third gate TCP 14C, is supplied with a third gate voltage VG3, including the gate high voltage VGH and the gate low voltage VGL, that is reduced in an amount proportional to the sum of the first, second, and third line resistances (a+b+c) of the first to third LOG type signal lines LVG1 to LVG3, connected in series. The third gate voltage VG3 is applied to the gate lines of the third horizontal line block (C) via the third gate driver IC 16.
Since differences between the gate voltages VG1 to VG3 exist, differences in brightness between the first to third horizontal line blocks A to C connected to one of the first to third gate driver ICs 16 also exist, which are manifested as a horizontal line 6. This causes the picture display area 21 to appear divided, thereby deteriorating a picture quality of the LCD. Progressing from the first gate driver IC to the third gate driver IC, the line resistances (a, b, c) of the LOG type signal line LVG add to one another. Accordingly, the first gate voltage VG1 is greater than the second gate voltage VG2, and the second gate voltage VG2 is greater than the third gate voltage VG3.
While the difference in gate voltages applied by the gate driver ICs 16 can be compensated for by independently connecting the plurality of LOG type gate voltage transmission lines to corresponding gate driver ICs 16 and by decreasing the cross section of the lines in proportion to the length of the transmission line, the outer area of the lower substrate 2, where the LOG type signal line group 26 is formed, is limited. Accordingly, it becomes not only difficult to provide a plurality of LOG type signal lines, but there is a physical limit as to how large the cross section of a transmission line can be initially formed.
Accordingly, the compensation of gate voltage differences using line resistors, without changing the design of the LOG type signal line group 26 formed within the limited space, has been proposed in accordance with the principles of the present invention.